Doped aluminum oxide dielectrics

ABSTRACT

Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

RELATED APPLICATION

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/792,777 (allowed), filed Feb. 23, 2001 and titled, “DOPEDALUMINUM OXIDE DIELECTRICS,” which is commonly assigned and incorporatedby reference in its entirety herein.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to dielectrics forintegrated circuit devices, and in particular to the development ofdoped aluminum oxide dielectrics and devices containing suchdielectrics.

BACKGROUND OF THE INVENTION

[0003] To meet demands for faster processors and higher capacitymemories, integrated circuit (IC) designers are focusing on decreasingthe minimum feature size within integrated circuits. By minimizing thefeature size within an integrated circuit, device density on anindividual chip increases exponentially, as desired, enabling designersto meet the demands imposed on them. As modern silicon devices becomesmaller and the minimum feature size of CMOS (complementary metal oxidesemiconductor) devices approaches and goes below the 0.1 μm regime, verythin gate insulators of thickness less than 2 nm (20A) will be requiredto keep the capacitance of the DRAM (dynamic random access memory)capacitor cell in the range of 30 fF. This capacitance value isgenerally required to provide immunity to radiation, soft errors and anominal signal-to-noise ratio.

[0004] Silicon dioxide (SiO₂), the most commonly used insulator, showshigh leakage current density at thicknesses in the range of 20 nm due toband-to-band tunneling current or Fowler-Nordheim tunneling current. Asa result, high-k dielectric films such as aluminum oxide (Al₂O₃),tantalum pentoxide (Ta₂O₅) and titanium dioxide (TiO₂) have receivedconsiderable interest as gate insulators to replace silicon dioxide.

[0005] While aluminum oxide has shown considerable promise, its porousnature leads to drawbacks. It has been noted that aluminum oxideporosity is generally the result of an acicular crystalline structureand that some pores may extend through the entire thickness of analuminum oxide layer having a thickness on the order of 100 nm. Studieshave also shown that exposure to humid atmospheres and even normalatmospheric conditions leads to a build-up of water in the pores ofaluminum oxide films. This water build-up results in a loss ofdielectric properties. In particular, water build-up can lead to adecrease in breakdown voltage of several orders of magnitude.

[0006] For the reasons stated above, and for other reasons stated belowthat will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternative aluminum oxide structures and methods of their production.

SUMMARY

[0007] Aluminum oxide has shown considerable promise as a dielectricmaterial for integrated circuit devices. However, its porous natureleads to drawbacks, in that the pores can adsorb water, thus resultingin a detrimental impact on the dielectric properties of the aluminumoxide material. The various embodiments of the invention involve aporous aluminum oxide layer having dopant material embedded in its poresand subsequently converted to a dielectric form. The doped aluminumoxide layer is formed sequentially to facilitate formation of ahigh-purity aluminum oxide layer and subsequently sealing its pores toimpede water adsorption. Doped aluminum oxide layers of variousembodiments are especially suited for use as gate dielectric layers,intergate dielectric layers and capacitor dielectric layers in variousintegrated circuit devices.

[0008] For one embodiment, the invention provides a doped aluminum oxidelayer. The doped aluminum oxide layer includes an aluminum oxide layerhaving pores on a surface and a dopant material filling the pores. Thedopant material is silicon, zirconium, hafnium or titanium and isapplied to the aluminum oxide layer subsequent to a formation of thealuminum oxide layer.

[0009] For another embodiment, the invention provides a doped aluminumoxide layer. The doped aluminum oxide layer includes an aluminum oxidelayer having pores on a surface and voids below the surface. The dopedaluminum oxide layer further includes a dopant material of silicon,zirconium, hafnium or titanium. The pores contain at least a portion ofthe dopant material, and the voids are free of the dopant material.

[0010] For yet another embodiment, the invention provides a dielectriclayer. The dielectric layer includes an aluminum oxide layer havingpores on a surface and a second dielectric material embedded in thepores of the aluminum oxide layer. The second dielectric material isformed of a dopant material of silicon, zirconium, hafnium or titanium.The dopant material is embedded in the pores of the aluminum oxide layerand subsequently converted to its dielectric form.

[0011] For still another embodiment, the invention provides a dielectriclayer. The dielectric layer includes an aluminum oxide layer havingpores on a surface and voids below the surface. The dielectric layerfurther includes a second dielectric material. The second dielectricmaterial is formed by depositing a dopant material in the pores andtreating the dopant material to convert it to its dielectric form. Thepores contain at least a portion of the second dielectric material,while the voids are free of the second dielectric material.

[0012] For one embodiment, the invention provides a method of forming adielectric layer. The method includes forming a porous aluminum oxidelayer on a substrate and forming a dopant layer on the porous aluminumoxide layer. The dopant layer contains a dopant material of silicon,zirconium, hafnium or titanium. The method further includes convertingthe dopant material to a dielectric form. For a further embodiment,excess dopant material is removed from the surface of the aluminum oxidelayer prior to converting the dopant material to its dielectric form.

[0013] Further embodiments of the invention include apparatus andmethods of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIGS. 1A-1C are cross-sectional views of a doped aluminum oxidelayer taken during various processing stages in accordance with anembodiment of the invention.

[0015]FIG. 1D is a cross-sectional view of one deposition system for usein forming the aluminum oxide layer of FIGS. 1A-1C.

[0016]FIG. 2 is a cross-sectional view of a field-effect transistor inaccordance with an embodiment of the invention.

[0017]FIG. 3 is a cross-sectional view of a floating-gate field-effecttransistor in accordance with an embodiment of the invention.

[0018]FIG. 4 is a cross-sectional view of a portion of a DRAM memoryarray in accordance with an embodiment of the invention.

[0019]FIG. 5 is a simplified block diagram of an integrated circuitmemory device in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

[0020] In the following detailed description of the present embodiments,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical or mechanical changes may be madewithout departing from the scope of the present invention. The termswafer or substrate used in the following description include any basesemiconductor structure. Examples include silicon-on-sapphire (SOS)technology, silicon-on-insulator (SOI) technology, thin film transistor(TFT) technology, doped and undoped semiconductors, epitaxial layers ofa silicon supported by a base semiconductor structure, as well as othersemiconductor structures well known to one skilled in the art.Furthermore, when reference is made to a wafer or substrate in thefollowing description, previous process steps may have been utilized toform regions/junctions in the base semiconductor structure, and theterms wafer and substrate include the underlying layers containing suchregions/junctions. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims and equivalents thereof.

[0021]FIGS. 1A-1C depict fabrication of a doped aluminum oxide layer 108as a portion of an integrated circuit device in accordance with oneembodiment of the invention. FIGS. 1A-1C are cross-sectional views takenduring various processing stages.

[0022] In FIG. 1A an aluminum oxide layer 102 is formed on the substrate100. The aluminum oxide layer 102 is porous, containing one or morepores 104 on the surface. Note that pores 104 may extend through thealuminum oxide layer 102 to the substrate 100 such as pore 104 a. Voids103 may be contained in the aluminum oxide layer 102. Voids 103 arespaces between grains or crystals of aluminum oxide that do not extendto the surface of the aluminum oxide layer 102.

[0023] The substrate 100 may be a monocrystalline silicon material. Forexample, the substrate 100 may be a wafer of monocrystalline siliconhaving a [100] orientation. The substrate 100 is generally asemiconductor material doped to a conductivity type, such as a p-typeconductivity. As an example, the substrate 100 may be implanted with ap-type dopant, such as boron, followed by an anneal to produce a p-typesubstrate. As another example, the substrate 100 may have an n-typeconductivity, such as a silicon substrate doped using an n-type dopantsuch as phosphorus or arsenic. Alternatively, the substrate 100 may besome other layer of an integrated circuit device. For example, thesubstrate 100 may be a floating gate layer of a floating-gatefield-effect transistor. The substrate 100 may further include othersemiconductor, conductor or insulator layers.

[0024] The aluminum oxide layer 102 is formed through physical vapordeposition (PVD) techniques to produce a high-purity film. The PVDtechniques preferably are evaporation techniques using a high-purityaluminum or alumina source, such as zone-refined aluminum or sapphirecrystals. Such sources are significantly more pure than traditionalpowder targets commonly used in PVD sputtering techniques. For oneembodiment, the aluminum or alumina source has a purity in excess of99.99%. For a further embodiment, the aluminum or alumina source has apurity of approximately 99.9999%. Evaporation PVD techniques are wellunderstood in the art. Examples include thermal evaporation,electron-beam evaporation and ion-beam-assisted deposition. For aluminumsources, formation of an aluminum oxide layer 102 would require reactiveevaporation of the aluminum source in an oxygen-containing atmosphere, atechnique well known in the art.

[0025] The level of porosity of the aluminum oxide layer 102 may beexpressed as packing density. Packing density, p, is a measure of theextent individual grains or crystals of aluminum oxide occupy the grossvolume of the aluminum oxide layer 102 relative to voids or pores.Packing density has been defined in literature by the relation:

p=σ/ρ _(sc) h

[0026] where:

[0027] σ is the surface density of the layer;

[0028] ρ_(sc) is the volume density of the skeleton of the film; and

[0029] h is the geometric height of the film

[0030] As a first approximation, ρ_(sc) can be equated to the density ofsapphire, or 3.99 g/cm³.

[0031] Wide ranges of packing density are readily producible in aluminumoxide films as has been reported in the literature. See, e.g., Brik, E.B., “Effect of Substrate Temperature on Density of Aluminum OxideFilms,” Opt. Mekh. Promst. 57 (1), pp. 50-52 (January 1990) (reportingpacking density values ranging from 0.66 to 0.95). Vacuum-depositedaluminum oxide films on cold substrates are generally amorphous while anacicular crystalline structure appears at higher substrate temperatures.Id.

[0032] The degree of packing density can be easily controlled throughthe use of ion bombardment or plasma activation during deposition. Asdemonstrated in one study, packing density of electron-beam evaporatedaluminum oxide films can be controlled through oxygen ion bombardmentduring deposition. In this study, the index of refraction, and thereforethe film density, first rose and then decreased with increasing ioncurrent density for substrate temperatures between 70° C. and 250° C.See, Franzen, W., et al., “Study of Oxygen-Ion-Beam-Assisted EvaporatedAluminum Oxide Films,” Mat. Res. Soc. Symp. Proc., Vol. 29, pp. 825-30(1993). Similarly, the addition of plasma activation during filmdeposition has been shown to produce a glassy fracture and densermicrostructure than film deposition without plasma activation. See,Zywitzki, O., et al., “Effect of Plasma Activation on the PhaseTransformations of Aluminum Oxide,” Surface and Coatings Tech. 76-77,pp. 745-762 (1995).

[0033] The aluminum oxide layer 102 is a porous layer having a packingdensity of less than 1. For one embodiment, the aluminum oxide layer 102has a packing density of between approximately 0.65 and 0.999. For afurther embodiment, the aluminum oxide layer 102 has a packing densityof between approximately 0.85 and 0.999.

[0034] The aluminum oxide layer 102 is doped, subsequent to depositionor formation, to improve the dielectric properties of the resultantfilm. In FIG. 1B, a dopant layer 106 is formed on the aluminum oxidelayer 102. The dopant layer 106 contains a dopant material. For oneembodiment, the dopant layer 106 contains silicon (Si). For additionalembodiments, the dopant layer 106 may contain zirconium (Zr), titanium(Ti) or hafnium (Hf). The dopant layer 106 fills pores 104 of thealuminum oxide layer 102 and covers the surface of the aluminum oxidelayer 102.

[0035] The dopant layer 106 may be formed by PVD or chemical vapordeposition (CVD) techniques as a blanket deposition. As one example, asilicon-containing dopant layer 106 may be formed by CVD using silane(SiH₄) or other suitable silicon precursor. For one embodiment, a dilutesilane feed, e.g., 2% silane in nitrogen (N₂), is pulsed into a reactionchamber for deposition of the dopant layer 106 on the aluminum oxidelayer 102. The dopant layer 106 is deposited to a thickness less than orequal to an average diameter of the pores 104 using a substratetemperature of approximately 300° C. to 350° C. This process is similarto the passivation of a copper substrate by silicide formation asprovided in Hymes, S., et al., “Passivation of Copper by SilicideFormation in Dilute Silane,” Mat. Res. Soc. Conf. Proc., ULSI-VII, pp.425-31 (1992). For a further embodiment, the dopant layer 106 isdeposited to a thickness of less than approximately 5 nm.

[0036] In FIG. 1C, excess dopant material is optionally removed from thesurface of the aluminum oxide layer 102. This leaves islands 107 ofdopant material, i.e., that material filling the pores 104, embedded inthe surface of the aluminum oxide layer 102. For one embodiment, removalof excess dopant involves exposing the surface of the dopant layer 106to a mild ion beam, such as a beam of argon (Ar) ions. Removal of excessdopant material can eliminate the series capacitance effects of twoadjacent dielectric layers.

[0037] For one embodiment, the aluminum oxide layer 106 has a packingdensity such that the dopant material embedded in the surface of thealuminum oxide layer 102, e.g., the islands 107 of dopant material,constitutes approximately 0.1% to 30% by weight of the doped aluminumoxide layer 108. For a further embodiment, the aluminum oxide layer 106has a packing density such that the dopant material embedded in thesurface of the aluminum oxide layer 102 constitutes approximately 0.1%to 10% by weight of the doped aluminum oxide layer 108.

[0038] Whether or not the excess dopant material is removed, the dopantmaterial is subsequently treated to homogenize the doped aluminum oxidelayer 108. Such treatment of the dopant material can include oxidationor nitridation to convert the dopant material to its oxide or nitrideform appropriate to impart dielectric properties to the dopant material.

[0039] For one embodiment, the dopant material is oxidized by rapidthermal annealing in an oxidizing atmosphere, such as anoxygen-containing atmosphere. The oxygen-containing atmosphere shouldpreferably contain sufficient oxygen to oxidize all of the dopantmaterial. For example, for a dopant layer 106 containing silicon, theoxygen-containing atmosphere should contain sufficient oxygen to convertall of the silicon, i.e., the dopant layer 106 or the islands 107 ofdopant material, to silicon dioxide. For other embodiments, the treateddopant material includes zirconium dioxide (ZrO₂), hafnium dioxide(HfO₂) or titanium dioxide (TiO₂), formed by oxidation of zirconium,hafnium or titanium dopant materials, respectively.

[0040] For another embodiment, the dopant material is nitrided by rapidthermal nitridation in a nitrogen-containing atmosphere. Thenitrogen-containing atmosphere should preferably contain sufficientnitrogen to nitridate all of the dopant material. For example, for adopant layer 106 containing silicon, the nitrogen-containing atmosphereshould contain sufficient nitrogen to convert all of the silicon, i.e.,the dopant layer 106 or the islands 107 of dopant material, to siliconnitride (Si₃N₄).

[0041]FIG. 1D is a cross-sectional view of one deposition system 112 foruse in forming an aluminum oxide layer 102 as described above. Thedeposition system 112 includes a chamber 114 for containing thesubstrate 100 under vacuum. A crucible 118 holds an aluminum or aluminasource 122. The source 122 is heated, e.g., by resistive heating orelectron-beam bombardment, to produce vaporized species 124 fordeposition on a surface of the substrate 100. If the vaporized species124 are aluminum atoms, they may be reacted with an oxygen-containingatmosphere within the chamber 114 to produce aluminum oxide.

[0042] An ion gun 126 may be included in the deposition system 112 toprovide ion beams 132 impinging on the surface of the substrate 100. Theion beams 132 generally impinge on the surface of substrate 100 at someangle, e.g., approximately 20°. A gas inlet 128 provides an ion sourcefor the ion gun 126, e.g., oxygen or argon to produce oxygen ions andargon ions, respectively. For plasma activation of the vaporized species124, a plasma 134 is formed between the crucible 118 and the substrate100.

[0043] The doped aluminum oxide layer 108 may be used as a dielectriclayer in a variety of integrated circuit devices subsequent toconverting the dopant material to its dielectric form. Example usesinclude gate dielectric layers for field-effect transistors, intergatedielectric layers for floating-gate transistors and capacitor dielectriclayers. The doped aluminum oxide layer 108 differs from layers ofaluminum oxide that are doped during deposition in that the dopantmaterial is not dispersed throughout the layer. The evaporation PVDtechniques facilitate use of high-purity sources. The evaporation PVDtechniques further facilitate control over the degree of porosity, andthus the dopant level, of the resultant layer.

[0044]FIG. 2 is a cross-sectional view of a field-effect transistorhaving a gate stack 245 overlying a substrate 200, a first source/drainregion 235 in the substrate 200 adjacent a first sidewall of the gatestack 245, and a second source/drain region 240 in the substrate 200adjacent a second sidewall of the gate stack 245. The gate stack 245includes a gate dielectric layer 205. The gate dielectric layer 205contains a doped aluminum oxide layer in accordance with an embodimentof the invention. Gate stack 245 further includes a conductor, oftencontaining a conductively-doped polysilicon layer 210 overlying the gatedielectric layer 205, a metal layer 220, and a conductive barrier layer215 interposed between the polysilicon layer 210 and the metal layer220. Insulative cap layer 225 and sidewall spacers 230 insulate andprotect the gate stack 245 from other adjacent layers. The field-effecttransistor of FIG. 2 may be an access transistor of a DRAM memory cell,having the first source/drain region 235 coupled to a bit line and thesecond source/drain region 240 coupled to a cell capacitor.

[0045]FIG. 3 is a cross-sectional view of a floating-gate field effecttransistor, or simply a floating-gate transistor, having a gate stack345 overlying a substrate 300, a first source/drain region 335 in thesubstrate 300 adjacent a first sidewall of the gate stack 345, and asecond source/drain region 340 in the substrate 300 adjacent a secondsidewall of the gate stack 345. The gate stack 345 includes a gatedielectric layer 305. For one embodiment, the gate dielectric layer 305contains a doped aluminum oxide layer in accordance with an embodimentof the invention. Gate stack 345 further includes a floating-gate layer311, a control-gate layer 321 and an intergate dielectric layer 317interposed between the floating-gate layer 311 and the control-gatelayer 321. For one embodiment, the intergate dielectric layer 317contains a doped aluminum oxide layer in accordance with an embodimentof the invention.

[0046] Insulative cap layer 325 and sidewall spacers 330 insulate andprotect the gate stack 345 from other adjacent layers. The floating-gatetransistor of FIG. 3 may be a flash memory cell, having the firstsource/drain region 335 coupled to a bit line of a flash memory arrayand having at least the control-gate layer 321 coupled to a word line ofthe flash memory array. The second source/drain region 340 is generallycommonly coupled among all memory cells of the flash memory array or aportion of the flash memory array.

[0047]FIG. 4 is a cross-sectional view of a portion of a DRAM memoryarray. The memory array includes word lines 445 a as access transistorsoverlying the substrate 400. Word lines 445 b are formed overlyingisolation regions 495 and are coupled to access transistors for memorycells outside the plane of the drawing. Each memory cell of the DRAMmemory array includes an access transistor and a cell capacitor.

[0048] Each word line 445 a has a first source/drain region 435 coupledto a bit line 485 through a bit-line contact 490. Each word line 445 afurther has a second source/drain region 440 coupled to a first plate455 of a cell capacitor, such as through a conductive plug 450. The cellcapacitor has a second plate 470 and a cell dielectric layer 465interposed between the first plate 455 and the second plate 470. Thesecond plate 470, or cell plate, is generally shared among all memorycells of the memory array or a portion of the memory array. Insulatinglayer 480 provides structural support to the cell capacitors as well aselectrical isolation of adjacent conductive layers.

[0049] For one embodiment, the cell dielectric layer 465 contains adoped aluminum oxide layer in accordance with an embodiment of theinvention. For another embodiment, the word lines 445 a contain a dopedaluminum oxide gate dielectric layer in accordance with an embodiment ofthe invention.

[0050]FIG. 5 is a simplified block diagram of an integrated circuitmemory device 500 in accordance with an embodiment of the invention. Thememory device 500 may include a DRAM device or a flash memory device.The memory device 500 includes an array of memory cells 502, an addressdecoder 504, row access circuitry 506, column access circuitry 508,control circuitry 510, and Input/Output (I/O) circuitry 512. For a DRAMmemory device, the memory array 502 contains memory cells having anaccess transistor coupled between a bit line and a capacitor. For aflash memory device, the memory array 502 contains flash memory cellshaving a floating-gate transistor coupled to a bit line.

[0051] The memory device 500 can be coupled to a processor 514 or othermemory controller for accessing the memory array 502. The memory device500 coupled to a processor 514 forms part of an electronic system. Someexamples of electronic systems include personal computers, peripheraldevices, wireless devices, digital cameras, personal digital assistants(PDAs) and audio recorders.

[0052] The memory device 500 receives control signals across controllines 516 from the processor 514 to control access to the memory array502. Access to the memory array 502 is directed to one or more targetmemory cells in response to address signals received across addresslines 518. Once accessed in response to the control signals and theaddress signals, data is written to or read from the memory cells acrossDQ lines 520.

[0053] The memory cells of the memory array 502 are generally arrangedin rows and columns with a memory cell located at each intersection of abit line and a word line. Those memory cells coupled to a single wordline are generally referred to as a row of memory cells while thosememory cells coupled to a single bit line are generally referred to as acolumn of memory cells. The array of memory cells 502 includes at leastone memory cell having a gate dielectric layer, an intergate dielectriclayer or a capacitor dielectric layer in accordance with the invention.

[0054] It will be appreciated by those skilled in the art thatadditional circuitry and control signals can be provided, and that thememory device of FIG. 5 has been simplified to help focus on theinvention. It will be understood that the above description of a memorydevice is intended to provide a general understanding of the memory andis not a complete description of all the elements and features of atypical memory device.

[0055] As recognized by those skilled in the art, memory devices of thetype described herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. Integrated circuits are typically repeatedmultiple times on each substrate. The substrate is further processed toseparate the integrated circuits into dies as is well known in the art.

[0056] The foregoing figures were used to aid the understanding of theaccompanying text. However, the figures are not drawn to scale andrelative sizing of individual features and layers are not necessarilyindicative of the relative dimensions of such individual features orlayers in application. Accordingly, the drawings are not to be used fordimensional characterization.

CONCLUSION

[0057] Aluminum oxide has shown considerable promise as a dielectricmaterial for integrated circuit devices. However, its porous natureleads to drawbacks in that the pores can adsorb water, thus resulting ina detrimental impact on the dielectric properties of the aluminum oxidematerial. The various embodiments of the invention involve a porousaluminum oxide layer having dopant material embedded in its pores andsubsequently converted to a dielectric form. The doped aluminum oxidelayer is formed sequentially to facilitate formation of a high-purityaluminum oxide layer and subsequently sealing its pores to impede wateradsorption. Doped aluminum oxide layers of various embodiments areespecially suited for use as gate dielectric layers, intergatedielectric layers and capacitor dielectric layers in various integratedcircuit devices.

[0058] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.For example, other materials, shapes, deposition techniques and removaltechniques may be utilized with the invention. Accordingly, thisapplication is intended to cover any adaptations or variations of theinvention. It is manifestly intended that this invention be limited onlyby the following claims and equivalents thereof.

What is claimed is:
 1. A doped aluminum oxide layer, comprising: analuminum oxide layer having pores on a surface; and a dopant materialfilling the pores; wherein the dopant material is selected from thegroup consisting of silicon, zirconium, hafnium and titanium; andwherein the dopant material is applied to the aluminum oxide layersubsequent to a formation of the aluminum oxide layer such that thedopant material is not dispersed throughout the aluminum oxide layer. 2.The doped aluminum oxide layer of claim 1, wherein the aluminum oxidelayer further includes voids below the surface and wherein the voids arefree of the dopant material.
 3. The doped aluminum oxide layer of claim1, wherein the aluminum oxide layer is formed by a method selected fromthe group consisting of thermal evaporation, electron-beam evaporationand ion-beam-assisted deposition.
 4. The doped aluminum oxide layer ofclaim 3, wherein a degree of porosity of the aluminum oxide layer iscontrolled during formation of the aluminum oxide layer using a methodselected from the group consisting of ion bombardment and plasmaactivation.
 5. The doped aluminum oxide layer of claim 3, wherein adegree of porosity of the aluminum oxide layer is controlled bybombarding the surface of the aluminum oxide layer with oxygen ionsduring formation.
 6. The doped aluminum oxide layer of claim 1, whereinthe aluminum oxide layer has a packing density between approximately0.65 and 0.999.
 7. The doped aluminum oxide layer of claim 1, whereinthe aluminum oxide layer has a packing density between approximately0.85 and 0.999.
 8. The doped aluminum oxide layer of claim 1, whereinthe dopant material constitutes approximately 0.1% to 30% by weight ofthe doped aluminum oxide layer.
 9. The doped aluminum oxide layer ofclaim 1, wherein the dopant material constitutes approximately 0.1% to10% by weight of the doped aluminum oxide layer.
 10. The doped aluminumoxide layer of claim 1, wherein the aluminum oxide layer has a degree ofporosity such that the dopant material filling the pores of the aluminumoxide layer constitutes approximately 0.1% to 30% by weight of the dopedaluminum oxide layer.
 11. The doped aluminum oxide layer of claim 1,wherein the aluminum oxide layer has a degree of porosity such that thedopant material filling the pores of the aluminum oxide layerconstitutes approximately 0.1% to 10% by weight of the doped aluminumoxide layer.
 12. The doped aluminum oxide layer of claim 1, wherein thedopant material is blanket deposited on the aluminum oxide layer. 13.The doped aluminum oxide layer of claim 12, wherein excess dopantmaterial is removed from the surface of the aluminum oxide layer. 14.The doped aluminum oxide layer of claim 13, wherein removing the excessdopant material comprises exposing the excess dopant material to an ionbeam.
 15. The doped aluminum oxide layer of claim 14, wherein exposingthe excess dopant material to an ion beam further comprises exposing theexcess dopant material to a beam of argon ions.
 16. The doped aluminumoxide layer of claim 12, wherein the dopant material is silicon formedby a chemical vapor deposition using dilute silane in nitrogen and asubstrate temperature of approximately 300° C. to 350° C.
 17. The dopedaluminum oxide layer of claim 12, wherein the dopant material isdeposited to a thickness less than or equal to an average diameter ofthe pores.
 18. A doped aluminum oxide layer, comprising: an aluminumoxide layer having pores on a surface, wherein the aluminum oxide layeris formed using an evaporation physical vapor deposition technique; anda dopant material filling the pores; wherein the dopant material isselected from the group consisting of silicon, zirconium, hafnium andtitanium; and wherein the dopant material is applied to the aluminumoxide layer subsequent to a formation of the aluminum oxide layer suchthat the dopant material is not dispersed throughout the aluminum oxidelayer.
 19. The doped aluminum oxide layer of claim 18, wherein a degreeof porosity of the aluminum oxide layer is controlled during formationof the aluminum oxide layer using a method selected from the groupconsisting of ion bombardment and plasma activation.
 20. The dopedaluminum oxide layer of claim 18, wherein the aluminum oxide layer has apacking density between approximately 0.65 and 0.999.
 21. The dopedaluminum oxide layer of claim 18, wherein the dopant materialconstitutes approximately 0.1% to 10% by weight of the doped aluminumoxide layer.
 22. The doped aluminum oxide layer of claim 18, wherein thealuminum oxide layer has a degree of porosity such that the dopantmaterial filling the pores of the aluminum oxide layer constitutesapproximately 0.1% to 30% by weight of the doped aluminum oxide layer.23. The doped aluminum oxide layer of claim 18, wherein the dopantmaterial is blanket deposited on the aluminum oxide layer.
 24. The dopedaluminum oxide layer of claim 23, wherein excess dopant material isremoved from the surface of the aluminum oxide layer.
 25. The dopedaluminum oxide layer of claim 23, wherein the dopant material isdeposited to a thickness less than or equal to an average diameter ofthe pores.
 26. A dielectric layer, comprising: an aluminum oxide layerhaving pores on a surface; and a second dielectric material embedded inthe pores of the aluminum oxide layer; wherein the second dielectricmaterial is formed of a dopant material selected from the groupconsisting silicon, zirconium, hafnium and titanium; and wherein thedopant material is embedded in the pores of the aluminum oxide layerafter formation of the aluminum oxide layer, such as not to disperse thedopant material throughout the aluminum oxide layer, and the dopantmaterial is subsequently converted to a dielectric form selected fromthe group consisting of an oxide form and a nitride form.
 27. Thedielectric layer of claim 26, wherein the aluminum oxide layer furthercontains voids below the surface and wherein the voids are free of thesecond dielectric material.
 28. The dielectric layer of claim 26,wherein the aluminum oxide layer is formed by a method selected from thegroup consisting of thermal evaporation, electron-beam evaporation andion-beam-assisted deposition.
 29. The dielectric layer of claim 28,wherein a degree of porosity of the aluminum oxide layer is controlledduring formation of the aluminum oxide layer using a method selectedfrom the group consisting of ion bombardment and plasma activation. 30.The dielectric layer of claim 28, wherein a degree of porosity of thealuminum oxide layer is controlled by bombarding the surface of thealuminum oxide layer with oxygen ions during formation.
 31. Thedielectric layer of claim 26, wherein the aluminum oxide layer has apacking density between approximately 0.65 and 0.999.
 32. The dielectriclayer of claim 26, wherein the aluminum oxide layer has a packingdensity between approximately 0.85 and 0.999.
 33. The dielectric layerof claim 26, wherein the dopant material embedded in the poresconstitutes approximately 0.1% to 30% by weight of the dielectric layer.34. The dielectric layer of claim 26, wherein the dopant materialembedded in the pores constitutes approximately 0.1% to 10% by weight ofthe dielectric layer.
 35. The dielectric layer of claim 26, wherein thealuminum oxide layer has a degree of porosity such that the dopantmaterial embedded in the pores constitutes approximately 0.1% to 30% byweight of the dielectric layer.
 36. The dielectric layer of claim 26,wherein the aluminum oxide layer has a degree of porosity such that thedopant material embedded in the pores constitutes approximately 0.1% to10% by weight of the dielectric layer.
 37. The dielectric layer of claim26, wherein the dopant material is blanket deposited on the aluminumoxide layer and subsequently treated to convert the dopant material toits dielectric form.
 38. The dielectric layer of claim 37, whereinexcess dopant material is removed from the surface of the aluminum oxidelayer prior to converting the dopant material to its dielectric form.39. The dielectric layer of claim 38, wherein removing the excess dopantmaterial comprises exposing the excess dopant material to an ion beam.40. The dielectric layer of claim 39, wherein exposing the excess dopantmaterial to an ion beam further comprises exposing the excess dopantmaterial to a beam of argon ions.
 41. The dielectric layer of claim 37,wherein the dopant material contains silicon formed by a chemical vapordeposition using dilute silane in nitrogen and a substrate temperatureof approximately 300° C. to 350° C., and wherein the silicon of thedopant material is converted to silicon dioxide using rapid thermalannealing in an oxygen-containing atmosphere.
 42. The dielectric layerof claim 37, wherein the dopant material is deposited to a thicknessless than or equal to an average diameter of the pores.
 43. Thedielectric layer of claim 26, wherein the dielectric layer is a gatedielectric layer of a field-effect transistor.
 44. The dielectric layerof claim 26, wherein the dielectric layer is an intergate dielectriclayer of a floating-gate field-effect transistor.
 45. The dielectriclayer of claim 26, wherein the dielectric layer is a capacitordielectric layer of a capacitor.
 46. A field-effect transistor,comprising: a gate stack overlying a substrate, wherein the gate stackincludes a gate dielectric layer having an aluminum oxide layer and asecond dielectric material embedded in a surface of the aluminum oxidelayer, wherein a dopant material is embedded in the surface of thealuminum oxide layer after a formation of the aluminum oxide layer,thereby not dispersing the dopant material throughout the aluminum oxidelayer, and the dopant material is subsequently treated to form thesecond dielectric material, and wherein the dopant material is selectedfrom the group consisting of silicon, zirconium, hafnium and titanium; afirst source/drain region in the substrate adjacent a first sidewall ofthe gate stack; and a second source/drain region in the substrateadjacent a second sidewall of the gate stack.
 47. The field-effecttransistor of claim 46, wherein the field-effect transistor is an accesstransistor for a memory cell of a dynamic random access memory device.48. The field-effect transistor of claim 46, wherein the field-effecttransistor is a floating-gate field-effect transistor.
 49. Thefield-effect transistor of claim 48, wherein the floating-gatefield-effect transistor is a flash memory cell of a flash memory device.50. The field-effect transistor of claim 46, wherein the seconddielectric material is a dielectric material selected from the groupconsisting of oxide forms of silicon, zirconium, hafnium and titanium,and nitride forms of silicon.
 51. The field-effect transistor of claim46, wherein the second dielectric material is a dielectric materialselected from the group consisting of silicon dioxide, zirconiumdioxide, hafnium dioxide, titanium dioxide and silicon nitride.
 52. Thefield-effect transistor of claim 46, wherein the aluminum oxide layer isformed by a method selected from the group consisting of thermalevaporation, electron-beam evaporation and ion-beam-assisted deposition.53. The field-effect transistor of claim 52, wherein a degree ofporosity of the aluminum oxide layer is controlled during formation ofthe aluminum oxide layer using a method selected from the groupconsisting of ion bombardment and plasma activation.
 54. Thefield-effect transistor of claim 46, wherein the aluminum oxide layerhas a packing density between approximately 0.66 and 0.999.
 55. Thefield-effect transistor of claim 46, wherein the dopant materialconstitutes approximately 0.1% to 30% by weight of the gate dielectriclayer.
 56. The field-effect transistor of claim 46, wherein the aluminumoxide layer has a degree of porosity such that the dopant materialembedded in the surface of the aluminum oxide layer constitutesapproximately 0.1% to 30% by weight of the gate dielectric layer. 57.The field-effect transistor of claim 46, wherein dopant material isformed by blanket depositing the dopant material on the surface of thealuminum oxide layer.
 58. The field-effect transistor of claim 57,wherein excess dopant material is removed from the surface of thealuminum oxide layer prior to treating the dopant material.
 59. Thefield-effect transistor of claim 57, wherein the second dielectricmaterial contains silicon dioxide formed by a chemical vapor depositionof silicon using dilute silane in nitrogen and a substrate temperatureof approximately 300° C. to 350° C., followed by rapid thermal annealingthe silicon in an oxygen-containing atmosphere.
 60. The field-effecttransistor of claim 57, wherein the dopant material is deposited to athickness less than or equal to an average diameter of the pores.
 61. Afloating-gate field-effect transistor, comprising: a gate stackoverlying a substrate, wherein the gate stack includes a control-gatelayer, a floating-gate layer and an intergate dielectric layerinterposed between the control-gate layer and the floating-gate layer,wherein the intergate dielectric layer has an aluminum oxide layer and asecond dielectric material embedded in a surface of the aluminum oxidelayer, wherein a dopant material is embedded in the surface of thealuminum oxide layer after a formation of the aluminum oxide layer suchas not to disperse the dopant material throughout the aluminum oxidelayer, and the dopant material is subsequently treated to form thesecond dielectric material, and wherein the dopant material is selectedfrom the group consisting of silicon, zirconium, hafnium and titanium; afirst source/drain region in the substrate adjacent a first sidewall ofthe gate stack; and a second source/drain region in the substrateadjacent a second sidewall of the gate stack.
 62. The floating-gatefield-effect transistor of claim 61, wherein the second dielectricmaterial is a dielectric material selected from the group consisting ofoxide forms of silicon, zirconium, hafnium and titanium, and nitrideforms of silicon.
 63. The floating-gate field-effect transistor of claim61, wherein the second dielectric material is a dielectric materialselected from the group consisting of silicon dioxide, zirconiumdioxide, hafnium dioxide, titanium dioxide and silicon nitride.
 64. Thefloating-gate field-effect transistor of claim 61, wherein the aluminumoxide layer is formed by a method selected from the group consisting ofthermal evaporation, electron-beam evaporation and ion-beam-assisteddeposition.
 65. The floating-gate field-effect transistor of claim 64,wherein a degree of porosity of the aluminum oxide layer is controlledduring formation of the aluminum oxide layer using a method selectedfrom the group consisting of ion bombardment and plasma activation. 66.The floating-gate field-effect transistor of claim 61, wherein thealuminum oxide layer has a packing density between approximately 0.66and 0.999.
 67. The floating-gate field-effect transistor of claim 61,wherein the dopant material constitutes approximately 0.1% to 30% byweight of the gate dielectric layer.
 68. The floating-gate field-effecttransistor of claim 61, wherein the aluminum oxide layer has a degree ofporosity such that the dopant material embedded in the surface of thealuminum oxide layer constitutes approximately 0.1% to 30% by weight ofthe gate dielectric layer.
 69. The floating-gate field-effect transistorof claim 61, wherein dopant material is formed by blanket depositing thedopant material on the surface of the aluminum oxide layer.
 70. Thefloating-gate field-effect transistor of claim 69, wherein excess dopantmaterial is removed from the surface of the aluminum oxide layer priorto treating the dopant material.
 71. The floating-gate field-effecttransistor of claim 69, wherein the second dielectric material containssilicon dioxide formed by a chemical vapor deposition of silicon usingdilute silane in nitrogen and a substrate temperature of approximately300° C. to 350° C., followed by rapid thermal annealing the silicon inan oxygen-containing atmosphere.
 72. The floating-gate field-effecttransistor of claim 69, wherein the dopant material is deposited to athickness less than or equal to an average diameter of the pores. 73.The floating-gate field-effect transistor of claim 61, wherein thefloating-gate field-effect transistor is a flash memory cell of a flashmemory device.
 74. A capacitor, comprising: a first capacitor plate; asecond capacitor plate; and a dielectric layer interposed between thefirst capacitor plate and the second capacitor plate, wherein thedielectric layer includes an aluminum oxide layer and a seconddielectric material embedded in a surface of the aluminum oxide layer,wherein a dopant material is embedded in the surface of the aluminumoxide layer after a formation of the aluminum oxide layer, thereby notdispersing the dopant material throughout the aluminum oxide layer, andthe dopant material is subsequently treated to form the seconddielectric material, and wherein the dopant material is selected fromthe group consisting of silicon, zirconium, hafnium and titanium. 75.The capacitor of claim 74, wherein the second dielectric material is adielectric material selected from the group consisting of oxide forms ofsilicon, zirconium, hafnium and titanium, and nitride forms of silicon.76. The capacitor of claim 74, wherein the second dielectric material isa dielectric material selected from the group consisting of silicondioxide, zirconium dioxide, hafnium dioxide, titanium dioxide andsilicon nitride.
 77. The capacitor of claim 74, wherein the aluminumoxide layer is formed by a method selected from the group consisting ofthermal evaporation, electron-beam evaporation and ion-beam-assisteddeposition.
 78. The capacitor of claim 77, wherein a degree of porosityof the aluminum oxide layer is controlled during formation of thealuminum oxide layer using a method selected from the group consistingof ion bombardment and plasma activation.
 79. The capacitor of claim 74,wherein the aluminum oxide layer has a packing density betweenapproximately 0.66 and 0.999.
 80. The capacitor of claim 74, wherein thedopant material constitutes approximately 0.1% to 30% by weight of thegate dielectric layer.
 81. The capacitor of claim 74, wherein thealuminum oxide layer has a degree of porosity such that the dopantmaterial embedded in the surface of the aluminum oxide layer constitutesapproximately 0.1% to 30% by weight of the gate dielectric layer. 82.The capacitor of claim 75, wherein dopant material is formed by blanketdepositing the dopant material on the surface of the aluminum oxidelayer.
 83. The capacitor of claim 82, wherein excess dopant material isremoved from the surface of the aluminum oxide layer prior to treatingthe dopant material.
 84. The capacitor of claim 82, wherein the seconddielectric material contains silicon dioxide formed by a chemical vapordeposition of silicon using dilute silane in nitrogen and a substratetemperature of approximately 300° C. to 350° C., followed by rapidthermal annealing the silicon in an oxygen-containing atmosphere. 85.The capacitor of claim 82, wherein the dopant material is deposited to athickness less than or equal to an average diameter of the pores. 86.The capacitor of claim 74, wherein the capacitor is a cell capacitor ofa memory cell of a dynamic random access memory device.
 87. Anelectronic system, comprising: a processor; and a memory device coupledto the processor; wherein at least one of the processor and the memorydevice contain a dielectric layer having a porous aluminum oxide layerand a second dielectric material embedded in pores of the porousaluminum oxide layer; wherein the second dielectric material is formedof a dopant material selected from the group consisting silicon,zirconium, hafnium and titanium; and wherein the dopant material isembedded in the pores of the porous aluminum oxide layer after formationof the porous aluminum oxide layer such that the dopant material is notdispersed throughout the porous aluminum oxide layer, and the dopantmaterial is subsequently converted to a dielectric form.